One goal of semiconductor manufacturing is to produce smaller integrated semiconductor devices with advantages of less power consumption and higher performance, a smaller footprint. In many applications, semiconductor wafers including integrated semiconductor devices, such as micro-electro-mechanical system (MEMS) devices, microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs) formed thereon are made as thin as possible to reduce package height for forming the smaller integrated semiconductor devices.
To reduce substrate thickness of the device wafer, the back surface of the device wafer undergoes a thinning process, such as a back grinding or a chemical mechanical polishing (CMP). As a result, the thinned device wafer is vulnerable and susceptible to cracking and breakage during handling and manufacturing processes. To reduce the potential for damage, a carrier wafer is typically affixed to the device wafer prior to the thinning process of the device wafer in order to provide additional structural support during the subsequent handling and manufacturing processes.
Typically, the carrier wafer is affixed to the device wafer by a bonding process exerting bonding pressure on the bonded wafers. However, since the device wafers may be bowed and bent in an undesired radius ratio due to the process-induced stress, thus an unsmooth contact wave of bonding front propagating outwards from the center of the bonded wafers and moving to the edge thereof may occur. As a result, void and gases can be trapped between the bonded wafers by the bonding process, and the device wafer may be more likely damaged during the subsequent thinning process of the device wafer.
Therefore, there is a need of providing an advanced integrated semiconductor device and a method for fabricating the same to obviate the drawbacks and problems encountered from the prior art.